
PIC18F2X1X/4X1X
DS39636D-page 152
2009 Microchip Technology Inc.
TABLE 15-3:
REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
RCON
IPEN
SBOREN(2)
—
RI
TO
PD
POR
BOR
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
PIR2
OSCFIF
CMIF
—
BCLIF
HLVDIF
TMR3IF
CCP2IF
PIE2
OSCFIE
CMIE
—
BCLIE
HLVDIE
TMR3IE
CCP2IE
IPR2
OSCFIP
CMIP
—
BCLIP
HLVDIP
TMR3IP
CCP2IP
TRISB
PORTB Data Direction Control Register
TRISC
PORTC Data Direction Control Register
TRISD
PORTD Data Direction Control Register
TMR1L
Timer1 Register Low Byte
TMR1H
Timer1 Register High Byte
T1CON
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
TMR2
Timer2 Register
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
PR2
Timer2 Period Register
TMR3L
Timer3 Register Low Byte
TMR3H
Timer3 Register High Byte
T3CON
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
CCPR1H
Capture/Compare/PWM Register 1 High Byte
CCP1CON
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
ECCP1AS
ECCPASE ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0 PSSBD1(1) PSSBD0(1)
PWM1CON
PRSEN
PDC6(1)
PDC5(1)
PDC4(1)
PDC3(1)
PDC2(1)
PDC1(1)
PDC0(1)
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1:
These bits are unimplemented on 28-pin devices and read as ‘0’.
2:
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled